1. Field of the Invention
This invention relates to a static memory in which a polysilicon thin film transistor is used as a load element of each memory cell.
2. Description of the Related Art
Recently, a static memory (SRAM), which has polysilicon thin film transistors (hereinafter abbreviated as TFTs) in place of high-resistance load elements constituted by a polysilicon layer, has been developed. The SRAM memory cell having a TFT is located between a complete CMOS memory cell and a memory cell having a high-resistance load element made of a polysilicon layer. Hence, this is a memory cell of the next generation having the advantages of both types of the memory cell. More particularly, the SRAM memory cell can be integrated as high as the latter, and consumes as low power in the static state and operates stably as the former.
The equivalent circuit of the SRAM memory cell having TFTs is shown in FIG. 1. One ends of transfer gates Q1 and Q2 are respectively connected to bit lines BL and BL, and the other ends thereof, to memory nodes A and B, respectively. The gates of the transfer gates are connected to a word line WL. The drains of an n-channel MOS transistor Q3 and a p-channel TFT Q4 are connected to a memory node A. The gates of transistors Q3 and Q4 are connected to a memory node B. The source of the transistor Q3 is connected to the earth potential V.sub.SS, and the source of the transistor Q4 to the source potential V.sub.CC. Similarly, the drains of an n-channel MOS transistor Q5 and a p-channel TFT Q6 are connected to the memory node B. The gates of the transistors Q5 and Q6 are connected to the node A. The source of the transistor Q5 is connected to the earth potential V.sub.SS, and the source of the transistor Q6 to the source potential V.sub.CC.
In the above-described memory cell, the transistors Q3 and Q4, and the transistors Q5 and Q6 respectively constitute complementary MOS inverters. The TFT is used as a load element for each of these complementary MOS inverters. Since the TFT serves as a transistor, when the TFT is in an OFF state, substantially no current flows in the memory cell, and when the TFT is in an ON state, a current flows which is much larger than in the case where the conventional high resistance load element is used in the memory cell.
There are two types among the SRAM memory cells having TFTs as load elements. The first type is shown in FIGS. 2A and 2B and the second type is shown in FIGS. 3A and 3B.
FIG. 2A is a pattern plan view showing a structure of the memory cell and FIG. 2B is a cross sectional view taken along line B--B' of FIG. 2A. As these figures show, the SRAM cell comprises a p-type semiconductor region 51; a field insulating film 52; an n.sup.+ diffusion region 53 serving as a source or drain region of the n-channel MOS transistor; a first polysilicon layer 54 serving as the gate electrode of the n-channel MOS transistor and the gate electrode of the p-channel TFT gate electrode; a second thin polysilicon layer 55 serving as a channel region and source and drain regions of the p-channel TFT; a channel region 56 of the TFT formed in the second polysilicon layer 55, to which substantially impurity concentration is low; a silicide layer 57 serving as an earth wiring; a silicide layer 58 serving as a main word line; an aluminum layer 59 serving as a first bit line BL; and an aluminum layer 60 serving as a second bit line BL.
In the above-described structure, as shown in FIGS. 2A and 2B, the channel of the n-channel MOS transistor extends in the same direction as that of the TFT. In other words, the channel regions of the n-channel MOS transistor and the TFT extend horizontally (FIG. 2A). In the TFT, since the channel, source and drain region are formed above the gate electrode, the source and drain regions cannot be self-aligned with the gate electrode, unlike in an ordinary MOS transistor in which the channel, source and drain regions are formed below the gate electrode. In particular, in manufacturing the TFT, it is impossible to use the gate electrode as a mask for forming a channel region, when ions are injected to form source and drain regions. For this reason, the channel length of a TFT must be longer and accordingly the memory size is larger than in an n-channel MOS transistor in which the source and drain regions can be formed in a self-aligning manner. To solve this drawback, offsets can be provided in the memory cell as shown in FIGS. 2A and 2B. However, this method is disadvantageous because the allowance for alignment is small, resulting in difference in the characteristic of the TFTs. Therefore, the method is not of practical use to manufacture an SRAM memory cell.
FIG. 3A is a pattern plan view showing a structure of the memory cell and FIG. 3B is a cross sectional view taken along the line C--C' of FIG. 3A. As is illustrated in FIGS. 3A and 3B, this SRAM memory cell comprises a p-type semiconductor region 71; a field insulating film 72; an n.sup.+ -diffusion region 73 (not shown in FIG. 3A) serving as a source or drain region of the n-channel MOS transistor; a first polysilicon layer 74 serving as a gate electrode of the n-channel MOS transistor; a second polysilicon layer 75 serving as a gate electrode of a p-channel TFT; a third thin polysilicon layer 76 serving as a channel region and source and drain regions of the p-channel TFT; and a channel region 77 of the TFT formed in the third polysilicon layer 76, in which substantially impurity concentration is low and which is kept at a high resistance. The first polysilicon layer is used as both a word line WL and an earth wiring, and the third polysilicon layer is used as a wiring for conducting the source potential V.sub.CC. The n.sup.+ -diffusion region is not shown in FIG. 3A.
In the above-described structure, in addition to the gate electrode 74 of the n-channel MOS transistor, the gate electrode 75 of the TFT is formed above the n-channel MOS transistor. The third thin polysilicon layer 76 serving as the channel region and the source and drain regions of the TFT are formed thereon. The structure is similar to that of FIGS. 2A and 2B in that the TFT cannot be formed in a self-aligning manner. However, it is different in that the channel of the TFT extends perpendicularly to that of the n-channel MOS transistor, as is clearly shown in FIGS. 3A and 3B. In other words, the channel of the n-channel MOS transistor extends perpendicularly to the plane of FIG. 3B, whereas the channel of the TFT extends horizontally. For this reason, the channel length of the TFT can be sufficiently long regardless of the channel length of the n-channel MOS transistor, thus overcoming the drawback due to the small alignment allowance.
However, as is shown in FIG. 3B, the structure is very complicated because of the three polysilicon layers. Moreover, one memory cell has seven contact holes to connect the polysilicon layers to one another, in addition to the contact holes connecting each of the polysilicon layers to the bit lines and the word lines. Further, the gate oxide film of the TFT must be formed of an interlayer film accumulated on the polysilicon layer. The accumulated film is inferior to a thermal oxide film in terms of the characteristics such as the number of pin holes, the Withstanding voltage, and the uniformity. Also, it is difficult to form the film thin.
The conventional SRAM memory cell shown in FIG. 2 has the following drawbacks: (1) the channel length of the TFT, which is not a self-aligning element, cannot be sufficiently long; (2) it is difficult to form a uniform TFT; and (3) since the interlayer accumulating film formed between the polysilicon layers is used as a gate oxide film of the TFT, it is difficult to form the accumulating film thin.
The conventional SRAM memory cell shown in FIG. 3 has the following drawbacks: (1) a complicated manufacturing technique is required to form the memory cell because of the three-layers polysilicon structure; (2) seven contact holes are required for interconnection in the memory cell; and (3) since the interlayer accumulating film formed between the polysilicon layers is used as a gate oxide film of the TFT, it is difficult to form the accumulating film thin.